1. Technical Field
The present invention relates in general to data processing, and in particular, to input/output (I/O) in a data processing system.
2. Description of the Related Art
A data processing system may include multiple processing elements and multiple input/output adapters (IOAs) to support connections to communication networks, storage devices and/or storage networks, and peripheral devices. In such data processing systems, the hardware resources of the data processing system may be logically partitioned into multiple, non-intersecting sets of resources, each controlled by a respective one of multiple possibly heterogeneous operating system instances. The operating systems concurrently execute on this common hardware platform in their respective logical partitions (LPARs) under the control of system firmware, which is referred to as a virtual machine monitor (VMM) or hypervisor. Thus, the hypervisor allocates each LPAR a non-intersecting subset of the resources of the data processing system, and each operating system instance in turn directly controls its distinct set of allocable resources, such as regions of system memory and IOAs.
In any environment including multiple IOAs, it is desirable to isolate IOAs so that each IOA can only obtain access to the resources allocated to it. Isolating IOAs promotes reliability, availability and serviceability of the data processing system, and is especially important in environments supporting hardware virtualization (or logical partitioning), so that IOAs can be individually allocated to different logical partitions (LPARs) and so that any IOA errors be isolated to the particular partition to which the IOA is allocated. For example, for Peripheral Component Interconnect (PCI) buses, if an IOA in one LPAR activates the System Error (SERR) signal, the system must make the SERR signal visible to all other LPARs absent some additional control. Making I/O errors visible across LPAR boundaries requirement is, of course, contrary to the definition and intent of logical partitioning.
One solution that addresses the partitioning problem with PCI errors is to require assignment of all IOAs connected to one PCI Host Bridge (PHB) to the same LPAR partition. However, this restriction mandates a high resource granularity for IOAs that is not very useful or flexible. Ideally, IOAs should be allocable to different LPARs regardless of the PHB to which the IOA is connected. Alternative solutions include the use of specially designed bridge chips external to the PHBs as described in U.S. Pat. No. 6,643,727 or incorporating additional logic and data structures to enforce partitioning between IOAs in differing LPARs within PHBs as described in U.S. Pat. No. 7,398,427.
As also appreciated by the present disclosure, it would be desirable to reduce the size of data structures within PHBs utilized in handling routine messages, such as DMA messages and I/O error message.